The present disclosure relates to interfacing an integrated circuit (IC or chip) with an external device, and more specifically, to level shifting an (input/output) I/O data signal to an intermediate voltage domain.
As silicon technology advances, the sustainable voltage for CMOS devices continues to decrease. While decreasing operating voltages reduce power and allow for denser logic, chip to chip communication via I/O circuits may still need to support legacy interface voltages (e.g., 3.3V LVTTL JEDEC Spec JESD8-B). However, 22 nm technology and future technology typically support 1.5V and lower devices.
One solution is to stack output devices which enable lower power chips to communicate using the legacy interface voltages. While stacking two output devices permits chips made in technologies such as 45 or 32 nm that support 1.8V devices to communicate with legacy voltages, this technique does not work for 22 nm and future fabrication techniques.